What's next

Nothing on this page is built. It is listed so you know where you still need the vendor IDE or another tool. Items that wait on a vendor document or a vendor contact are marked so.

Verification

• Run every Vivado, Quartus, Libero SoC and Radiant path against the real vendor tool, through the verification kits, and publish the results.
• Program and debug on real boards: open-flow boards through openFPGALoader, and the vendor evaluation boards (SP701 or AC701, an Intel board, a PolarFire kit, a CertusPro-NX board).
• Run the module on Windows, and check the file watcher for new project folders on macOS and Windows.
• Measure elaboration, lint, CDC, state machine extraction, schematics, builds, timing and the waveform viewer on a design of tens of thousands of cells and a waveform of about 1 GB, and publish a performance table.

Functions that still need the vendor IDE

• Quartus Signal Tap: creating and editing .stp files (Intel documents no format or batch writer).
• Quartus Power and Thermal Calculator, or Early Power Estimator, run from the Editor (no documented batch interface).
• Libero part list in the New Project wizard (waits on a Microchip source).
• Libero SmartDebug: probe insertion and DDR debug; parsing the active probe and device status output; the SerDes BER counter read and the plot_eye file.
• Libero Identify RTL instrumentor (documented as a GUI flow only).
• Radiant part list in the New Project wizard (waits on a Lattice source).
• Radiant Physical Designer: placement and routing in the device view (no documented placement export).
• Radiant Power Calculator.
• Running a Reveal Analyzer trigger from the Editor (no documented batch command); Reveal trigger codes beyond == and != and radices beyond binary and hex.

Project and settings

• Forms for Vivado's general, synthesis, implementation and bitstream settings, and for Quartus's Settings dialog (today: hdl.json with completion).
• Vivado synthesis and implementation strategy options that the .xpr stores as internal indexes.
• The remaining fields of Vivado's Elaboration settings page.
• Vivado IP status table and the IP cache.
• A Quartus view of IP components and design units of their own; resource counts for Altera parts in the New Project wizard.
• Value pickers for the full Quartus assignment catalogue in the Assignment Editor.
• Radiant implementations other than the active one.
• A licence status view for Vivado, Quartus, Libero and Radiant, and warnings when a device needs a paid edition.

Editing and design views

• A published supported SystemVerilog subset, a permissively usable front end evaluated on real SystemVerilog (interfaces and modports), and a clear message when elaboration fails instead of a blank view.
• Semantic rename, references and refactoring across the design.
• Vivado IP and block design contents in the Design Hierarchy; Altera IP elaborated in the RTL Viewer.
• Vivado's own elaboration (synth_design -rtl) for the RTL schematic with UNISIM primitives and IP.
• A post-mapping level in the Quartus technology map; Synplify Pro's RTL view.
• VHDL enum_encoding, and Verilog-to-VHDL generic overrides through the GHDL plugin.
• Language templates read from the vendor installs' own template catalogues, and every vendor shortcut checked against the vendor's documentation.

Simulation and waveforms

• Code coverage from XSim.
• Post-synthesis and timing simulation on Riviera-PRO, Xcelium and VCS from Vivado; Quartus gate-level simulation; Libero post-layout simulation.
• VUnit waveforms on NVC.
• Reading Vivado's .wdb (waits on an AMD export path or a partner route).
• Search by value in the waveform viewer.

Timing and clock domain crossings

• Recognise Gray-coded pointer synchronisers (the Cummings asynchronous FIFO) as safe in the RTL crossings view, and handshake, toggle-pulse and enable-qualified synchronisers.
• CDC waivers for the RTL view, stored in the project with reasons, glob matching and stale waivers reported.
• Related clocks (PLL outputs and dividers from one source, clock mux outputs, gated clocks, declared synchronous groups), reset domain crossings and reconvergence.
• Hold slack and TNS for the open flow; hold and TNS in the Vivado build summary itself (they are available in the design session today).
• Fmax in the Quartus build summary; plain Quartus warnings and message suppression rules for Quartus.
• Multi-line -group editing, set_bus_skew and set_max_delay -datapath_only columns in the Vivado constraints editor; virtual-clock and source-synchronous cases in the Timing Constraints Wizard.
• Labels on open-flow Fmax and slack as nextpnr estimates, with source lines on mid-path names.

I/O and floorplanning

• Differential pairs placed as pairs, and drive and slew editors, in the I/O planner.
• Noise margins from Report Noise drawn on the package.
• The I/O planning project's own DRC run in Vivado; clock planning and use per clock region.
• Quartus Interface Planner's own window (dragging transceiver, EMIF and IOPLL periphery to sites, its plan file); placing PLLs by hand.
• Device blocks drawn for Quartus and Libero (neither exports a block listing).
• Legible pin numbers on assigned pins in both themes, a bank legend, and BGA packages checked.

Builds and runs

• Vivado runs in parallel, and Vivado -bin_file and readback file options.
• Out-of-context synthesis for Vivado IP and whole block designs.
• Quartus Pro block-based incremental flow in the kit; Quartus's own Design Assistant waiver file.
• Quartus resource use per entity and the compilation report's other panels.
• Libero SmartPower activity files and scenarios; Libero SPI directory and auto-update images.
• Power estimates for the open FPGA flow, and switching activity from cocotb testbenches.

IP and systems

• Standard Edition MegaWizard .qip variations in Customize IP.
• Radiant IP parameters with the IP's own labels, ranges and choices.
• Vivado block designs: Run Block Automation, moving cells into a hierarchy, Vivado's canvas layout, and board interface automation.
• Platform Designer Pro system edits in the kit, and the instance parameter form inside a system.
• SmartDesign bus-interface pin grouping and slices, and macros and HDL cores in Add Component.

Programming and hardware debug

• Vivado Lab Edition discovery; a configuration memory blank check and readback to file; BPI flash tested.
• Tandem with Field Updates.
• A Quartus kit step for configuration flash; .cof multi-image and Pro .rpd files.
• A JTAG transport and virtual I/O for the built-in logic analyser.

ASIC

• Pad rings for SKY130.
• IR drop from flip-chip bumps.
• A noise analysis that simulates the nets the crosstalk screen does not clear, with their aggressors' timing windows.
• Equivalence results that state their assumptions in the UI and warn about retimed netlists; the crosstalk and IR drop screens labelled as screens, never "clean".

Integration

• Submitting HDL hardware operations (such as loading a bitstream) to Neural Inverse Govern's policy check. Today the confirmations described on each page are the control.
• Generated output (logic analyser core, wrappers, constraints) stating that it is yours to ship.