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Industries / Mobility and devices

Close timing sooner, on the tools you already license.

For FPGA, verification and implementation engineers. Your EDA tools and licences stay as they are.

Standards
DO-254 · ISO 26262
Languages
Verilog, SystemVerilog, VHDL
Open tools
Verilator, Icarus, GHDL, Yosys, nextpnr
Vendor tools
Vivado, Quartus, Libero, Radiant
Deployment
Self-hosted, your cloud or air-gapped

What your team gets

Write, simulate and synthesise without leaving the editor.

Govern features are in use today. Domain modules are pre-release; their state is listed under Tools and formats.

Language supportVerilog, SystemVerilog and VHDL with navigation and diagnostics.
Lint and simulationErrors in the editor and testbenches with pass or fail per test, waveforms beside the code.
Formal and cocotbSymbiYosys properties and cocotb testbenches in the Testing view.
Synthesis and timingPlace and route with utilisation and timing reports for iCE40, ECP5, Gowin and AMD 7-series.
Vendor flowsVivado, Quartus, Libero and Radiant driven in batch mode, with reports in the same views.
Bitstreams stay with peopleThe HDL and FPGA template denies agents device programming and bitstream edits; timing and pin constraint changes wait for a named approver.

Who uses it

One environment for every role on the team.

FPGA engineersWrite, lint and simulate RTL with results in the editor.
Verification engineersRun testbenches and formal properties with pass or fail per test and waveforms beside the code.
Implementation engineersSynthesise, place and route, and read utilisation and timing.
Lab engineersProgram boards once a change is approved.

Tools and formats

What the HDL module handles, and how far each is verified.

The module is behind a setting, off by default, and offers itself once in a workspace with HDL sources.

FPGA, open flowLint, simulation, cocotb testbenches, formal verification, waveforms, synthesis and place and route. Verified on Linux. Programming a board is not yet run.Verilator · Icarus Verilog · GHDL · cocotb · SymbiYosys · Yosys · nextpnr · openFPGALoader · VCD · FST
AMD 7-series without VivadoArtix-7, Kintex-7, Spartan-7 and Zynq-7000 fabric built on the open flow. Verified on Linux by building a bitstream; not programmed on a board.Yosys · nextpnr-xilinx · Project X-Ray
Constraint filesChecked as they are edited against the elaborated design. Verified on Linux for placement constraints; clocks, delays and exceptions are not checked.PCF · LPF · CST · SDC · XDC
FPGA, vendor flowsThe vendor tools driven in batch mode, with their messages and timing and utilisation reports in the same views. Kit shipped or modelled: not yet run against the vendor tools.AMD Vivado · Intel Quartus · Microchip Libero SoC · Lattice Radiant

Domain modules are pre-release. Nothing is verified by a customer yet, and nothing is verified on Windows. Do not rely on a capability for production work until it is verified for your tools, versions and operating system. Product names belong to their owners.

How a change moves

A person decides before anything leaves the desk.

  1. Propose
    An engineer or agent drafts a change to RTL or constraints.
  2. Verify
    Your tools lint, simulate and build it.
  3. Approve
    A timing or pin constraint change waits for a named approver.
  4. Record
    Change, results and approval kept together in the audit record.

Standards

Evidence for your design assurance. The certification is yours.

DO-254Evidence toward DO-254: each implementation run kept with the commit it came from, and each RTL change with its review and approval.
ISO 26262Evidence toward ISO 26262: constraint changes reviewed by a named approver, and every change kept with its approval.

Neural Inverse provides evidence toward these standards. Certification stays with your organisation and assessor.

Rules you work under

What they ask, and what Neural Inverse gives you toward them.

We produce records your assessors and regulators can use. We never say a product makes you compliant; that stays with your organisation.

[Draft: to be approved by legal counsel before publication]

US export controls: the EARWhat it asksLicences for advanced computing items, semiconductor manufacturing items and the technology and software to design or make them, by destination and end use. Releasing controlled technology or source code to a foreign person, even inside the United States, can count as an export. BIS has revised these rules several times since October 2022, including in January 2026.What Neural Inverse gives youSelf-hosted, in-your-cloud and air-gapped deployments keep designs on infrastructure you control, with single sign-on, access control and a tamper-evident audit log of who did what.
ITARWhat it asksWhere a design is a defence article, such as some space and military parts, its technical data stays with authorised people and inside licensed boundaries.What Neural Inverse gives youSelf-hosted and air-gapped deployments keep controlled designs inside your boundary. Our hosted service is not offered for ITAR-controlled data.
Trade secretsWhat it asksUnder the US Defend Trade Secrets Act and the EU Trade Secrets Directive (2016/943), design data is protected as a trade secret only if you take reasonable steps to keep it secret.What Neural Inverse gives youData loss prevention on prompts and context, restricted work kept to models you host, and an audit log of every change and decision.

Questions

What semiconductors and fpga teams ask us first.

Does it work with our EDA tools and licences?

Yes. The HDL module drives the open tools and your vendor tools; your licences stay as they are. The open flow is verified on Linux; the Vivado, Quartus, Libero and Radiant flows are kit shipped or modelled and not yet run against the vendor tools.

Can it run on-premises or air-gapped?

Yes. Govern runs on your own servers, in your own cloud account or on a network with no internet access, with models served inside your network.

Can an AI agent program a device or change a bitstream?

No. The HDL and FPGA template denies agents device programming and bitstream edits; timing and pin constraint changes wait for a named approver.

Is Neural Inverse qualified to DO-254 or ISO 26262?

No. Govern gives evidence toward DO-254 and ISO 26262 for your design assurance. Tool qualification and certification stay with you and your assessor.

Products used

Neural Inverse Build →
Editor, Agents and CLI with the domain tools your engineers need.
Neural Inverse Govern →
Policy, approvals and audit for every AI tool your teams use.

Product names belong to their owners.

Talk to our team.

Neural Inverse is available by request. We work with your engineering, security and procurement teams from the first conversation.

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Semiconductors and FPGA · Neural Inverse