Firmware & Embedded

Open with Cmd+Alt+F. Purpose-built for embedded engineers working with microcontrollers.

Source: src/vs/workbench/contrib/neuralInverseFirmware/

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MCU Database

357+ MCU variants across 11 manufacturers:

Each entry includes: core type, max clock, flash/RAM sizes, FPU/MPU/DSP flags, GPIO count, peripheral list, memory map, and common dev boards.

Clock Constraint Tables

Every MCU family has a validated clock constraint table in engine/clockTree/clockTreeValidatorService.ts. Constraints include max SYSCLK, PLL input/VCO ranges, and APB divider restrictions. Families covered include TM4C, MSP430, XMC1/4, S32K, Apollo, MAX32, CC26xx, BL60x, Nuvoton, STM32C0/H5/MP1/U5/WB, PIC32, PIC24/18/16, RISC-V, and all FPGA families — no silent fallthrough to generic defaults.

Linker Script Generator

engine/memory/linkerScriptGenerator.ts produces correct .ld / .icf / .sct linker scripts for all 148 MCU families, with accurate flash/RAM origins and sizes. Notable specifics:

• AURIX: PMU cached PFlash starts at 0xA0000000 (not 0x80000000)
• MSP430 Harvard: Flash 0xC000, RAM 0x0200
• Each family uses its own verified base addresses — no STM32 defaults for other vendors

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SVD Register Maps

CMSIS-SVD files are parsed on demand:

• Fetches SVD XML from CMSIS Pack Index or local cache
• Parses full peripheral trees with bit-field detail
• Handles derivedFrom inheritance at peripheral and register level
• Expands clusters and dimension arrays
• Default value inheritance (size, access, resetValue)

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Datasheet Intelligence

Drop a PDF datasheet and the agent extracts structured data:

1. Extraction — PDF parsed page by page
2. Classification — each page categorized (register map, timing, errata, pinout, electrical specs)
3. LLM Reclassification — uncertain pages verified with LLM
4. Caching — content-hash based, zero re-processing on re-open
5. Citations — all extracted data links back to source page numbers

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Hardware Instruments

The Instruments tab (firmwarePart.ts) provides four canvas-based panels for real hardware instruments. All panels use Canvas 2D or programmatic DOM (no innerHTML) to satisfy Trusted Types.

Logic Analyzer

File: engine/instruments/logicAnalyzer/logicAnalyzerService.ts

• Saleae Logic 2 — TCP automation API on port 10430
• Digilent WaveForms — dwfpy Python subprocess
• Canvas waveform renderer: dark navy (#1a1a2e) background, one row per channel, time-grid with labels
• Software protocol decoders (no dependency on Saleae's decoder API):
  • UART NRZ — start bit detection, configurable baud rate, data/parity/stop
  • I2C — SCL/SDA edge timing, address extraction, ACK/NACK, repeated start
  • SPI — CPOL/CPHA modes, CS framing, byte assembly
• Decoded frames rendered in a grid table below the waveform
• Raw samples stored in capture.rawSamples: Record<number, number[]> for offline re-decode

Power Analyzer

File: engine/instruments/powerAnalyzer/powerAnalyzerService.ts

• Nordic PPK2 — USB VID 1915 / PID C00A, nrfjprog + Python subprocess
• Joulescope JS110 / JS220 — joulescope Python subprocess
• PPK2-style current graph: dark (#0d1117) canvas, µA/mA Y-axis with auto-scale, min/max range band, avg line
• 6-cell stats bar: AVG / MIN / MAX / PEAK / ENERGY / CHARGE

Oscilloscope

File: engine/instruments/oscilloscope/oscilloscopeService.ts

• Siglent SDS800X HD — SCPI over LAN, port 5025
• mDNS LXI discovery + VOID_SCOPE_HOST env override for fixed IP
• CRT-style canvas (#001a00 background, phosphor green waveform)
• Trigger configuration (edge, level, source channel)
• Measurements bar: Pk-Pk, Mean, RMS

Combined Workflows

3-row grid with coordinated multi-instrument scenarios:

• Sleep current regression (PPK2 + GDB + Logic)
• I2C NACK hunt (Logic + GDB)
• Power-on sequence (scope trigger + logic capture)

Each workflow shows: instrument icon strip, center title/status dots/run button, right-side step list.

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RTT (Real-Time Transfer)

File: engine/serial/rttService.ts

SEGGER J-Link RTT streaming via SWD/JTAG — zero-overhead printf without a UART peripheral.

• JLinkExe backend — spawns JLinkExe subprocess with an RTT script file, streams stdout
  • Detects connection via NumUpBuffers, RTT enabled, Connected to target patterns
  • Parses multiple JLink output formats for RTT terminal data
  • Polls rtterminal read 0 every 100ms
• pylink backend — pylink-square Python subprocess, JSON-encoded frame stream, fallback if JLinkExe unavailable
• Multi-channel support (up to 32 channels, up + down)
• 10,000-line ring buffer per channel
• fw_rtt_start, fw_rtt_read, fw_rtt_write, fw_rtt_stop agent tools

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Agent Tools

Available in sidebar chat and Power Mode when a firmware project is detected:

Clock Codegen

fw_codegen_clock generates correct RCC/CMU/CGC init for every supported family. For unrecognized families it emits SDK-specific guidance rather than silently generating STM32 code.

GPIO Codegen

fw_codegen_gpio (inside codegenTools.ts) uses a per-architecture dispatch table. For families without an explicit handler, it generates architecture-appropriate pin config (e.g. RISC-V GPIO register writes, AVR DDR/PORT, PIC LAT/TRIS) instead of defaulting to STM32 HAL.

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Serial Monitor

Built-in serial port communication:

• Web Serial API for browser-based access
• 10,000-line ring buffer
• Baud rate auto-detection
• Debug probe auto-detection (ST-Link, J-Link, CMSIS-DAP, FTDI, CH340)
• Send/receive with timestamp

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Platform Knowledge Packs

Injected into every agent session when working on a supported platform:

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Build System Integration

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Contributing

Key files:

To add a new MCU family: add an entry to mcuDatabase.ts, add clock constraints to clockTreeValidatorService.ts, add linker origins to linkerScriptGenerator.ts, and add a codegen case to codegenTools.ts.

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