NeuralInverse CE — Firmware

Your AI already knows
the hardware.

An embedded development environment built into the IDE. MCU specs, register maps, datasheets, silicon errata, and compliance rules are in AI context the moment a session opens.

Download free Read the docs
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MCU variants in the built-in database
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Hardware agent tools, injected automatically
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Compliance frameworks
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LLM calls when reopening a cached PDF
Overview

Hardware context is loaded, not typed.

Open Firmware with Ctrl+Alt+F. NeuralInverse scans the workspace, detects the project type and MCU, and opens a session. From that point, every chat message, Power Mode agent call, and code completion runs with the full peripheral map, datasheet index, and active compliance standard already in context.

No copy-pasting register definitions. No switching to a browser to look up a bit field. No manually telling the AI which MCU you are using. The session carries that state for the entire IDE.

Project auto-detection — confidence scores
Firmware.inverse
Explicit manifest — always loaded
1.0
platformio.ini
PlatformIO project
0.9
*.ioc
STM32CubeMX project
0.9
sdkconfig
ESP-IDF project
0.85
prj.conf
Zephyr project
0.85
Cargo.toml
Rust embedded
0.8
CMakeLists.txt
Generic embedded project
0.6
SVD Register Maps

Every register, every bit field, in context.

The Registers tab shows a full peripheral tree from CMSIS-SVD data. Expand any peripheral to see registers and bit fields with names, access type, reset values, and descriptions. Hover over a register access in the editor and the SVD description appears inline.

Eight SVDs are bundled and load instantly: STM32F4, F7, H7, L4, G4, nRF52840, ESP32, RP2040. For everything else, the auto-fetcher pulls from posborne/cmsis-svd and caches for the session.

Registers — USART1
// USART1 base: 0x40011000 // CR1 offset: 0x00 UE bit 0 rw reset:0 // USART enable RE bit 2 rw reset:0 // Receiver enable TE bit 3 rw reset:0 // Transmitter enable RXNEIE bit 5 rw reset:0 // RXNE interrupt enable OVER8 bit 15 rw reset:0 // Oversampling x8 // BRR offset: 0x04 BRR bits 0-15 rw // Baud rate register // 84 MHz APB2, 115200 baud -> 0x1D4
Datasheet Intelligence

400-page reference manual.
Processed in 10 seconds.

Drop any PDF datasheet or reference manual into the Datasheets tab. A three-tier pipeline extracts and indexes every page in-process with no external dependencies and no network calls on first run.

T1
PDF parser
Custom FlateDecode decompressor. Extracts raw text and tables from every page. No network call, no external library.
T2
Heuristic classifier
Classifies each page by type with zero LLM calls: registers, timing tables, errata, pinout, memory map, electrical characteristics.
T3
LLM reclassifier
Runs only on ambiguous pages, capped at 150 per document. Authoritative SVD is used when a part number is matched.

Results are content-hash cached in .inverse/hardware-kb/. Commit this directory and your team opens with pre-processed datasheets at zero cost.

What gets extracted
Errata
All silicon errata items, queryable by symptom via fw_check_silicon_bug
Timing tables
Setup/hold times, propagation delays, and clock constraints for every peripheral
Register pages
Overlaid with authoritative SVD data when a part number is matched in the PDF
Electrical characteristics
Voltage/current limits, operating conditions, and absolute maximum ratings
MCU Database

357 variants. Select once, always in context.

Search by part number, family, or board name. The AI immediately has the core architecture, Flash/RAM sizes, peripheral map, and platform-specific guidance for every subsequent interaction.

STM32
Cortex-M0 to M33
All families: F0/F1/F2/F3/F4/F7/H7/L0/L1/L4/L5/G0/G4/U5/WB. Bundled SVDs for F4, F7, H7, L4, G4.
ESP32
Xtensa / RISC-V
ESP32, ESP32-S2/S3, ESP32-C3/C6, ESP32-H2. Bundled SVD for ESP32.
Nordic nRF
Cortex-M4 / M33
nRF52 series, nRF53 series, nRF91 series. Bundled SVD for nRF52840.
RP2040 / RP2350
Dual-core M0+
Raspberry Pi microcontrollers with PIO state machines. Bundled SVD for RP2040.
NXP / Renesas / TI
Multi-family
i.MX RT, S32K, RA/RX/RL78, MSP430, CC series. SVD auto-fetched.
Others
Custom SVD
Infineon XMC/PSoC, Silicon Labs EFM32, GigaDevice GD32. Any CMSIS-SVD file can be loaded manually.
Agent Tools

22 fw_* tools. Available the moment a session opens.

When Firmware is active, all 22 hardware tools are injected into Power Mode and the Agent automatically. No configuration. Filter by category below.

MCU
fw_get_mcu_info
Returns the active MCU variant, core, Flash/RAM sizes, and platform ID
fw_list_peripherals
Lists all peripherals in the active SVD with base addresses and descriptions
fw_search_mcu_database
Fuzzy-searches 357 variants by part number, family, or keyword
Registers
fw_get_register_map
Full register map for a named peripheral with bit field detail
fw_get_peripheral_config
Current configuration of a peripheral derived from SVD reset values
fw_get_clock_config
Clock tree configuration for the active MCU
Datasheets
fw_upload_datasheet
Triggers extraction of a PDF datasheet by path
fw_query_datasheet
Semantic search across all loaded datasheets
fw_get_errata
All errata items from loaded datasheets
fw_check_silicon_bug
Checks if a described behaviour matches a known silicon errata
fw_get_timing_constraints
Timing tables for a named peripheral or signal
Build
fw_build_project
Runs the build command for the detected project type
fw_flash_device
Flashes the built binary to the connected device
fw_binary_analysis
Section sizes and Flash/RAM usage as percentages against MCU spec
Serial
fw_read_serial
Latest N lines from the 10,000-line serial ring buffer with timestamps
fw_write_serial
Sends a string to the serial port
Debug
fw_start_debug_session
Starts a GDB server connection (OpenOCD, J-Link, pyocd, st-util, QEMU)
fw_send_gdb_command
Sends a raw GDB command and returns the response
fw_read_cpu_registers
All CPU register values: r0-r15, sp, lr, pc, xpsr
fw_read_memory
Reads memory at a given address and length
fw_write_memory
Writes bytes to a given memory address
fw_set_breakpoint
Sets a breakpoint by file:line or function name
Compliance

Safety standards enforced,
not just documented.

Active frameworks are shown in the Compliance tab and the IDE status bar. Every AI interaction is constrained by the active standard for the duration of the session. Set them in Firmware.inverse or from the Compliance tab without restarting.

MISRA C:2012 / 2023
Embedded C
Coding standard for safety-critical systems. Enforced across code generation, review, and inline suggestions.
CERT C
Secure coding
Guards against undefined behaviour, integer overflows, and memory safety errors.
IEC 62304
Medical
Medical device software lifecycle. Class-based safety requirements throughout development.
ISO 26262
Automotive
Automotive functional safety. ASIL-level requirements in code generation and analysis.
DO-178C
Avionics
Airborne software certification. Design assurance levels A through D.
IEC 61508
Industrial
Functional safety for industrial systems. SIL 1 through 4.
AUTOSAR
Automotive
Software architecture standard for automotive ECUs.
Platform Knowledge

The AI knows what trips people up on your platform.

Four built-in knowledge packs inject platform-specific rules, common mistakes, and undocumented constraints into every interaction when the corresponding MCU family is active.

STM32
ST Microelectronics
  • RCC clock enable patterns for every peripheral family
  • GPIO alternate function tables (AF0-AF15) per pin
  • HAL vs LL performance guidance
  • FLASH wait state rules by HCLK frequency band
  • DMA stream and channel assignment patterns
ESP32
Espressif
  • ESP-IDF task model and FreeRTOS core affinity
  • ADC2 / WiFi conflict and documented workaround
  • IRAM_ATTR placement for interrupt-critical code
  • menuconfig and Kconfig structure
  • Partition table layout and NVS usage
Nordic nRF
Nordic Semiconductor
  • Zephyr west build and board overlay patterns
  • EasyDMA RAM buffer alignment requirements
  • HFXO requirement for BLE radio
  • Devicetree pin assignment and peripheral binding
  • SoftDevice and nRF5 SDK memory constraints
RP2040 / RP2350
Raspberry Pi
  • Dual-core launch and inter-core FIFO patterns
  • PIO state machine authoring and side-set
  • QSPI XIP execution constraints and cache
  • USB 48 MHz clock requirement and PLL setup
  • DMA chaining and IRQ priority rules
Firmware.inverse

Commit the session.
Share the setup.

Place a Firmware.inverse file at the workspace root to lock the MCU, datasheets, SVD, and compliance frameworks. NeuralInverse scores confidence 1.0 and loads without prompting.

Commit the file. Every developer opens with the same MCU selected, the same datasheets indexed, and the same compliance frameworks active. No setup step.

Firmware.inverse
{ "mcu": "STM32F407VGT6", "board": "STM32F4-Discovery", "rtos": "FreeRTOS", "buildSystem": "cmake", "complianceFrameworks": [ "MISRA-C:2012" ], "datasheetPaths": [ ".inverse/hardware-kb/stm32f407-rm.pdf" ], "svdPath": ".inverse/STM32F407.svd" }